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NCP3066, NCV3066
APPLICATIONS
Figures 15 through 24 show the simplicity and flexibility
of the NCP3066. Two main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams. The demo boards have an input for a digital
dimming signal. You can provide a PWM signal to change
the average output current and reduce the LED brightness.
Figure 14 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3066 can be found at www.onsemi.com.
Parameter
ton
toff
t on
Step ? Down
Vout ) VF
Vin * VSWCE * Vout
ton
toff
Step ? Up
Vout ) VF * Vin
Vin * VSWCE
ton
toff
f
ton
toff
) 1
f
ton
toff
) 1
CT + 381.6 @ 10
C T
f osc
* 6
* 343
10 * 12
I L(avg)
Iout
Iout
ton
toff
) 1
I pk (Switch)
IL(avg) )
D IL
2
IL(avg) )
D IL
2
R SC
0.20
Ipk (Switch)
0.20
Ipk (Switch)
L
Vin * VSWCE * Vout
D IL
ton
Vin * VSWCE
D IL
ton
V ripple(pp)
D IL
1
8 f CO
2
) (ESR) 2
ton Iout
CO
) D IL
ESR
I out
V ref
R s
V ref
R s
9. V SWCE ? Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7 and 8.
10. V F ? Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
11. The calculated t on /t off must not exceed the minimum guaranteed oscillator charge to discharge ratio.
Figure 14. Design Equations
The Following Converter Characteristics Must Be Chosen:
V in ? Nominal operating input voltage.
V out ? Desired output voltage.
I out ? Desired output current.
D I L ? Desired peak ? to ? peak inductor ripple current. For maximum output current it is suggested that D I L be chosen to be
less than 10% of the average inductor current I L(avg) . This will help prevent I pk (Switch) from reaching the current limit threshold
set by R SC . If the design goal is to use a minimum inductance value, let D I L = 2(I L(avg) ). This will proportionally reduce
converter output current capability.
f ? Maximum output switch frequency.
V ripple(pp) ? Desired peak ? to ? peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor C O should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
http://onsemi.com
9
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